Test MP+dmb.sy+fri-rfi-addr-[fr-rf]-ctrlisb

AArch64 MP+dmb.sy+fri-rfi-addr-[fr-rf]-ctrlisb
"DMB.SYdWW Rfe Fri Rfi DpAddrdR FrLeave RfBack DpCtrlIsbdR Fre"
Cycle=Rfi DpAddrdR FrLeave RfBack DpCtrlIsbdR Fre DMB.SYdWW Rfe Fri
Relax=
Safe=Rfi Rfe Fri Fre DMB.SYdWW DpAddrdR DpCtrlIsbdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe Fri Rfi DpAddrdR FrLeave RfBack DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X6=z; 1:X9=x;
2:X1=z;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#1   ;
 STR W0,[X1] | MOV W2,#2           | STR W0,[X1] ;
 DMB SY      | STR W2,[X1]         |             ;
 MOV W2,#1   | LDR W3,[X1]         |             ;
 STR W2,[X3] | EOR W4,W3,W3        |             ;
             | LDR W5,[X6,W4,SXTW] |             ;
             | LDR W7,[X6]         |             ;
             | CBNZ W7,LC00        |             ;
             | LC00:               |             ;
             | ISB                 |             ;
             | LDR W8,[X9]         |             ;
Observed
    z=1; y=2; x=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X3=2; 1:X0=1;
and z=1; y=2; x=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X3=2; 1:X0=0;
and z=1; y=1; x=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X3=2; 1:X0=0;
and z=1; y=2; x=1; 1:X8=0; 1:X7=0; 1:X5=1; 1:X3=2; 1:X0=0;
and z=1; y=1; x=1; 1:X8=0; 1:X7=0; 1:X5=1; 1:X3=2; 1:X0=0;
and z=1; y=1; x=1; 1:X8=1; 1:X7=0; 1:X5=1; 1:X3=1; 1:X0=0;